? semiconductor components industries, llc, 2010 june, 2010 ? rev. 2 1 publication order number: ntd4909n/d ntd4909n power mosfet 30 v, 41 a, single n ? channel, dpak/ipak features ? low r ds(on) to minimize conduction losses ? low capacitance to minimize driver losses ? optimized gate charge to minimize switching losses ? these are pb ? free devices applications ? cpu power delivery ? dc ? dc converters maximum ratings (t j = 25 c unless otherwise noted) parameter symbol value unit drain ? to ? source voltage v dss 30 v gate ? to ? source voltage v gs 20 v continuous drain current (r ja ) (note 1) steady state t a = 25 c i d 12.1 a t a = 100 c 8.6 power dissipation (r ja ) (note 1) t a = 25 c p d 2.6 w continuous drain current (r ja ) (note 2) t a = 25 c i d 8.8 a t a = 100 c 6.2 power dissipation (r ja ) (note 2) t a = 25 c p d 1.37 w continuous drain current (r jc ) (note 1) t c = 25 c i d 41 a t c = 100 c 29 power dissipation (r jc ) (note 1) t c = 25 c p d 29.4 w pulsed drain current t p =10 s t a = 25 c i dm 167 a current limited by package t a = 25 c i dmaxpkg 60 a operating junction and storage temperature t j , t stg ? 55 to 175 c source current (body diode) i s 27 a drain to source dv/dt dv/dt 7.0 v/ns single pulse drain ? to ? source avalanche energy (t j = 25 c, v dd = 50 v, v gs = 10 v, l = 0.1 mh, i l(pk) = 24 a, r g = 25 ) e as 28 mj lead temperature for soldering purposes (1/8 from case for 10 s) t l 260 c stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above the recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may affect device reliability. 1. surface ? mounted on fr4 board using 1 in sq pad size, 1 oz cu. 2. surface ? mounted on fr4 board using the minimum recommended pad size. case 369aa dpak (bent lead) style 2 marking diagrams & pin assignments case 369d ipak (straight lead dpak) 30 v 8.0 m @ 10 v r ds(on) max 41 a i d max v (br)dss 12 m @ 4.5 v http://onsemi.com see detailed ordering and shipping information in the package dimensions sect ion on page 3 of this data sheet. ordering information 1 2 3 4 case 369ad ipak (straight lead) 1 2 3 4 n ? channel d s g yww 49 09ng 1 gate 2 drain 3 source 4 drain 4 drain 2 drain 1 gate 3 source 4 drain 2 drain 1 gate 3 source yww 49 09ng yww 49 09ng y = year ww = work week 4909n = device code g = pb ? free package 1 2 3 4
ntd4909n http://onsemi.com 2 thermal resistance maximum ratings parameter symbol value unit junction ? to ? case (drain) r jc 5.1 c/w junction ? to ? tab (drain) r jc ? tab 4.3 junction ? to ? ambient ? steady state (note 3) r ja 58.2 junction ? to ? ambient ? steady state (note 4) r ja 110 3. surface ? mounted on fr4 board using 1 in sq pad size, 1 oz cu. 4. surface ? mounted on fr4 board using the minimum recommended pad size. electrical characteristics (t j = 25 c unless otherwise noted) parameter symbol test condition min typ max unit off characteristics drain ? to ? source breakdown voltage v (br)dss v gs = 0 v, i d = 250 a 30 v drain ? to ? source breakdown voltage temperature coefficient v (br)dss /t j 15 mv/ c zero gate voltage drain current i dss v gs = 0 v, v ds = 24 v t j = 25 c 1.0 a t j = 125 c 10 gate ? to ? source leakage current i gss v ds = 0 v, v gs = 20 v 100 na on characteristics (note 5) gate threshold voltage v gs(th) v gs = v ds , i d = 250 a 1.0 1.7 2.2 v negative threshold temperature coefficient v gs(th) /t j 4.0 mv/ c drain ? to ? source on resistance r ds(on) v gs = 10 v i d = 30 a 6.5 8.0 m i d = 15 a 6.5 v gs = 4.5 v i d = 30 a 9.5 12 i d = 15 a 9.5 forward transconductance gfs v ds = 1.5 v, i d = 30 a 52 s charges and capacitances input capacitance c iss v gs = 0 v, f = 1.0 mhz, v ds = 15 v 1314 pf output capacitance c oss 487 reverse transfer capacitance c rss 17.4 total gate charge q g(tot) v gs = 4.5 v, v ds = 15 v, i d = 30 a 7.6 nc threshold gate charge q g(th) 2.1 gate ? to ? source charge q gs 4.3 gate ? to ? drain charge q gd 1.3 total gate charge q g(tot) v gs = 10 v, v ds = 15 v, i d = 30 a 17.5 nc switching characteristics (note 6) turn ? on delay time t d(on) v gs = 4.5 v, v ds = 15 v, i d = 15 a, r g = 3.0 11 ns rise time t r 21 turn ? off delay time t d(off) 17 fall time t f 2.7 turn ? on delay time t d(on) v gs = 10 v, v ds = 15 v, i d = 15 a, r g = 3.0 8.0 ns rise time t r 19 turn ? off delay time t d(off) 21 fall time t f 2.3 5. pulse test: pulse width 300 s, duty cycle 2%. 6. switching characteristics are independent of operating junction temperatures.
ntd4909n http://onsemi.com 3 electrical characteristics (t j = 25 c unless otherwise noted) parameter symbol test condition min typ max unit drain ? source diode characteristics forward diode voltage v sd v gs = 0 v, i s = 30 a t j = 25 c 0.9 1.1 v t j = 125 c 0.8 reverse recovery time t rr v gs = 0 v, dis/dt = 100 a/ s, i s = 30 a 30 ns charge time ta 16 discharge time tb 14 reverse recovery time q rr 20 nc package parasitic values source inductance (note 7) l s t a = 25 c 2.99 nh drain inductance, dpak l d 0.0164 drain inductance, ipak (note 7) l d 1.88 gate inductance (note 7) l g 4.9 gate resistance r g 1.0 2.0 7. assume terminal length of 110 mils. ordering information order number package shipping ? ntd4909nt4g dpak (pb ? free) 2500 / tape & reel ntd4909n ? 1g ipak (pb ? free) 75 units / rail ntd4909n ? 35g ipak trimmed lead (pb ? free) 75 units / rail ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d.
ntd4909n http://onsemi.com 4 typical characteristics 4.5 v figure 1. on ? region characteristics figure 2. transfer characteristics v ds , drain ? to ? source voltage (v) v gs , gate ? to ? source voltage (v) 4 3 2 1 0 0 10 20 30 50 60 80 90 4.5 4.0 3.5 3.0 2.5 2.0 0 20 40 60 80 figure 3. on ? resistance vs. v gs figure 4. on ? resistance vs. drain current and gate voltage v gs (v) i d , drain current (a) 9.0 8.0 7.0 10 6.0 5.0 4.0 3.0 0.004 0.006 0.008 0.010 0.012 0.016 0.018 0.020 85 75 65 55 45 35 25 15 0.004 0.005 0.006 0.007 0.010 0.011 0.012 0.014 figure 5. on ? resistance variation with temperature figure 6. drain ? to ? source leakage current vs. voltage t j , junction temperature ( c) v ds , drain ? to ? source voltage (v) 150 125 100 75 25 0 ? 25 ? 50 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 30 25 20 15 10 5 10 100 1000 10,000 i d , drain current (a) i d , drain current (a) r ds(on) , drain ? to ? source resistance ( ) r ds(on) , drain ? to ? source resistance ( ) r ds(on) , drain ? to ? source resistance (normalized) i dss , leakage (na) 40 70 v gs = 4.0 v 7 v 4.2 v 3.8 v 3.6 v 3.4 v 3.2 v 3.0 v 2.8 v 2.6 v 2.4 v t j = 25 c 10 v v ds = 10 v t j = 25 c t j = 125 c t j = ? 55 c 0.014 0.008 0.009 0.013 95 i d = 30 a t j = 25 c v gs = 4.5 v t j = 25 c v gs = 10 v 50 175 i d = 30 a v gs = 10 v v gs = 0 v t j = 85 c t j = 150 c t j = 125 c
ntd4909n http://onsemi.com 5 typical characteristics figure 7. capacitance variation figure 8. gate ? to ? source and drain ? to ? source voltage vs. total charge v ds , drain ? to ? source voltage (v) qg, total gate charge (nc) 25 20 15 10 30 5 0 0 500 1000 1500 2000 18 14 12 10 8 4 2 0 0 1.5 3.0 6.0 9.0 10.5 12.0 15.0 figure 9. resistive switching time variation vs. gate resistance figure 10. diode forward voltage vs. current r g , gate resistance ( ) v sd , source ? to ? drain voltage (v) 100 10 1 1 10 100 1000 0.8 0.2 1.0 0.6 0 0.4 0 5 10 15 20 25 30 figure 11. maximum rated forward biased safe operating area figure 12. maximum avalanche energy vs. starting junction temperature v ds , drain ? to ? source voltage (v) t j , starting junction temperature ( c) 100 10 1 0.1 0.1 1 10 100 1000 175 150 125 100 75 50 25 0 5 10 15 20 25 30 c, capacitance (pf) v gs , gate ? to ? source voltage (v) t, time (ns) i s , source current (a) i d , drain current (a) e as , single pulse drain ? to ? source avalanch e energy (mj) v gs = 0 v t j = 25 c c iss c oss c rss 61620 4.5 7.5 13.5 t j = 25 c qt qgs qgd v dd = 15 v v gs = 10 v i d = 30 a v dd = 15 v i d = 15 a v gs = 10 v t d(off) t d(on) t r t f t j = 25 c t j = 125 c v gs = 0 v v gs = 10 v single pulse t c = 25 c r ds(on) limit thermal limit package limit 100 s 10 s 10 ms 1 ms dc i d = 24 a
ntd4909n http://onsemi.com 6 typical characteristics figure 13. fet thermal response pulse time (sec) 0.01 0.001 0.0001 0.00001 0.000001 0.001 0.01 0.1 1 10 100 figure 14. gfs vs. id id (a) 45 40 30 25 15 10 5 0 0 10 20 30 40 50 60 r(t) ( c/w) gfs (s) 0.1 1 10 100 1000 10% duty cycle = 50% 20% 5% 2% 1% single pulse psi tab ? a 20 35 50
ntd4909n http://onsemi.com 7 package dimensions dpak (single guage) case 369aa ? 01 issue b b d e b3 l3 l4 b2 e m 0.005 (0.13) c c2 a c c z dim min max min max millimeters inches d 0.235 0.245 5.97 6.22 e 0.250 0.265 6.35 6.73 a 0.086 0.094 2.18 2.38 b 0.025 0.035 0.63 0.89 c2 0.018 0.024 0.46 0.61 b2 0.030 0.045 0.76 1.14 c 0.018 0.024 0.46 0.61 e 0.090 bsc 2.29 bsc b3 0.180 0.215 4.57 5.46 l4 ??? 0.040 ??? 1.01 l 0.055 0.070 1.40 1.78 l3 0.035 0.050 0.89 1.27 z 0.155 ??? 3.93 ??? notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: inches. 3. thermal pad contour optional within dimensions b3, l3 and z. 4. dimensions d and e do not include mold flash, protrusions, or burrs. mold flash, protrusions, or gate burrs shall not exceed 0.006 inches per side. 5. dimensions d and e are determined at the outermost extremes of the plastic body. 6. datums a and b are determined at datum plane h. 12 3 4 h 0.370 0.410 9.40 10.41 a1 0.000 0.005 0.00 0.13 l1 0.108 ref 2.74 ref l2 0.020 bsc 0.51 bsc a1 h detail a seating plane a b c l1 l h l2 gauge plane detail a rotated 90 cw style 2: pin 1. gate 2. drain 3. source 4. drain 5.80 0.228 2.58 0.102 1.60 0.063 6.20 0.244 3.00 0.118 6.17 0.243 mm inches scale 3:1 *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint*
ntd4909n http://onsemi.com 8 package dimensions 3.5 mm ipak, straight lead case 369ad ? 01 issue o b d l e e3 l2 b1 e 3x a1 a a1 a2 dim min max millimeters a 2.19 2.38 a1 0.46 0.60 a2 0.87 1.10 b 0.69 0.89 b1 0.77 1.10 d 5.97 6.22 e 2.28 bsc d2 4.80 ??? e 6.35 6.73 e2 4.70 ??? e3 4.45 5.46 l 3.40 3.60 l1 ??? 2.10 notes: 1.. dimensioning and tolerancing per asme y14.5m, 1994. 2.. controlling dimension: millimeters. 3. dimension b applies to plated terminal and is measured between 0.15 and 0.30mm from terminal tip. 4. dimensions d and e do not include mold gate or mold flash. t seating d2 e2 optional construction plane l1 l2 0.89 1.27 2x m 0.13 t d2 e2 ipak (straight lead dpak) case 369d ? 01 issue b style 2: pin 1. gate 2. drain 3. source 4. drain 123 4 v s a k ? t ? seating plane r b f g d 3 pl m 0.13 (0.005) t c e j h dim min max min max millimeters inches a 0.235 0.245 5.97 6.35 b 0.250 0.265 6.35 6.73 c 0.086 0.094 2.19 2.38 d 0.027 0.035 0.69 0.88 e 0.018 0.023 0.46 0.58 f 0.037 0.045 0.94 1.14 g 0.090 bsc 2.29 bsc h 0.034 0.040 0.87 1.01 j 0.018 0.023 0.46 0.58 k 0.350 0.380 8.89 9.65 r 0.180 0.215 4.45 5.45 s 0.025 0.040 0.63 1.01 v 0.035 0.050 0.89 1.27 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. z z 0.155 ??? 3.93 ??? on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5773 ? 3850 ntd4909n/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your loca l sales representative
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